During design of electronic circuits, for example digital circuits, on a register transfer level (RTL), or also in analog circuits various process, voltage and temperature corners need to be covered to ensure reliable operation of the circuit under various conditions. One of these corners is the so-called burn-in corner. This burn-in corner is used during the manufacturing process in a so-called burn-in test, where higher voltages and temperatures compared to normal operation are applied to the circuit to stress the circuit. By such tests, so-called “early life fails” may be filtered out from produced circuits, i.e. circuits with a probability to show some kind of malfunction quite early during actual use may be detected during the burn-in test.
This burn-in corner is an artificial corner for synthesis and timing closure (as it is not used during actual use of the circuit, but only during testing) and may cause problems during timing closure. Timing closure is the process by which a circuit design is modified to meet its timing requirements, in particular as regards setup times and hold times. Generally, setup times and hold times define time windows during which a signal state has to be maintained (for example before a sampling point indicated by a clock signal and thereafter to guarantee correct sampling). In particular, because of the high voltages involved in burn-in testing (for example about 1.5 times a normal supply voltage), various timings in a circuit typically shift to a very fast corner (i.e. small delays), which may cause hold time violation problems. Conventionally, this is fixed by adding additional hold time buffers as delay elements. Such delay elements are conventionally added to timing-critical paths e.g. during timing closure. However, adding these buffers may then cause timing problems in slow process corners which may require additional modifications to also cover the situation. For example, the hold time buffers may be needed to be scaled up to also meet setup requirements in slow corners.
Therefore, covering of this burn-in corner requires additional design efforts and leads to difficulties in timing closure. Moreover, the buffers added contribute to the current consumption of the final circuit, as the area, power and timing penalty of the additional hold time buffers are present in the final design, even though the buffers may be required only to ensure correct operation during one test during the manufacturing process.